1. Field of the Invention
The present invention relates to a structure and a manufacturing method of a semiconductor device, and more particularly, to a device and manufacturing method of a Bipolar CMOS (hereinafter BiCMOS) device suitable for attaining a high packing density.
2. Description of the Related Art
Generally, BiCMOS devices are widely used as high-speed switching elements, and are commonly used in output buffers.
As shown in the circuit diagram of FIG. 1, a conventional BiCMOS device is formed of an NMOS transistor and a PNP transistor.
In more detail, a signal is received via a gate G of the NMOS transistor Q.sub.1, and a drain D of the NMOS transistor Q.sub.1 is connected to a base B of a PNP transistor Q.sub.2. An emitter E of the PNP transistor Q.sub.2 is supplied with a constant voltage V.sub.DD, and a source S of the NMOS transistor Q.sub.1 and a collector C of the PNP transistor Q2 are connected so as to be commonly grounded. Thus, the signal is output via the emitter E of the PNP transistor Q.sub.2.
FIG. 2 is a sectional view showing the structure of the BiCMOS device of FIG. 1, and FIGS. 3a-3c are sectional views showing the steps of manufacturing such a device.
As shown in FIG. 2, two p-type wells 3 and 4 are formed in an n-type silicon substrate 1 so as to be separated from each other and electrically isolated by a field oxide layer 2, as illustrated. A gate oxide layer 5 with a gate electrode 6 thereon is formed on the p-type well 3, and high-concentration n-type impurity regions (n.sup.+) are formed on each side of the gate electrode 6 in the p-type well 3 so as to provide a source region and a drain region, respectively, of the NMOS transistor Q.sub.1. In a portion of the other p-type well 4, an n-type impurity region is implanted. In a portion of the n-type impurity region so formed, a high-concentration n-type impurity is implanted to form an n.sup.+ region which serves as a base B. In another portion of the n-type impurity region so formed, a high-concentration p-type impurity is implanted to form a p.sup.+ region which serves as the emitter E. In another portion of the p-type well 4, a high-concentration p-type impurity region p.sup.+ is implanted to serve as the collector C. On the surface of the n-type region between the base B and the emitter E, and on the surface of the p-type well 3 between the emitter E and collector C, an oxide layer 7 is formed to electrically isolate the emitter E, base B and collector C which form the PNP transistor Q.sub.2.
A method of manufacturing the BiCMOS device of FIGS. 1 and 2 will now be described.
As illustrated in FIG. 3a, the field oxide layer 2 is formed in the n-type silicon substrate 1 so as to define formation regions of the NMOS transistor Q.sub.1 and the PNP transistor Q.sub.2. Then, p-type well 3 and p-type collector 4 are formed in the NMOS transistor formation region and PNP transistor formation region, respectively, via p-type ion implantation and diffusion.
Referring to FIG. 3b, a gate oxide layer 5 is grown in the NMOS transistor region, and polysilicon is deposited to form a gate electrode 6 via a photolithography process. Low-concentration n-type ions are implanted into a predetermined region within the p-collector 4 of the PNP transistor Q.sub.2 to form the region n. Then high-concentration n-type (n.sup.+) ions are implanted into the p-type well 3 on each side of the gate electrode 6 to form a source region and a drain region, respectively.
As illustrated in FIG. 3c, high-concentration p-type (p.sup.+)ions are implanted into one side of the source region of the NMOS transistor Q.sub.1, as well as into a portion of the region n and a portion of the p-type well 4 so as to form the emitter E and collector C of the PNP transistor Q.sub.2. Then oxide layers 7 are grown between the base B, emitter E and collector C to electrically isolate these regions.
In the conventional BiCMOS device formed as above, the drain of the NMOS transistor Q.sub.1 is connected to the base B of the PNP transistor Q.sub.2, the gate electrode 6 of the NMOS transistor Q.sub.1 is set as an input terminal, and the emitter E of the PNP transistor Q.sub.1 is set as an output terminal so that the circuit as shown in FIG. 1 is obtained.
Therefore, the output electrode can be switched between two values by a signal supplied to the input electrode.
The conventional BiCMOS device, however, is disadvantageous in that a contact electrode is formed to serve as a terminal for each of the source S, drain D and gate G of the NMOS transistor and for each of the emitter E, collector C and base B of the PNP transistor Q.sub.2 so as to permit each terminal to be externally connected. As a result, it is difficult to increase the packing density and switching speed.